Phase locked loop circuits have long been utilized to provide output frequency stability of a voltage controlled oscillator by developing control voltages which drive the VCO to the desired frequency. Such phase locked loop circuits commonly use phase detectors to compare the output frequency, sampled at the VCO, with a known reference frequency. Early phase detectors utilized analog techniques whereby the reference frequency generated a ramp voltage which was then sampled in response to the variable frequency sampled at the VCO. More recently, digital techniques have been utilized for phase detection.
Early digital techniques were based on the assumption that if the error or difference between the actual and the desired frequency was sufficiently small, the loop was linear in its operation. However, a sufficient increase in the error will cause prior art phase locked loop circuits to drop out of lock. Similarly, if the initial error is great enough, the system may never achieve a lock-up condition. F. M. Gardner in "Phaselock Techniques", John Wiley and Sons, Inc., 1966, discusses this problem in depth, defining several acquisition terms for a typical high-gain second order loop. The "pull-in range" approximation of Chapter 4 (Equation 4-29, page 45) describes a maximum frequency error that the phase locked loop will tolerate before failing to acquire lock-up. As a result, there is a delta frequency change which, if exceeded, will result in the probability of a VCO never locking up. In the prior art, to overcome this problem, coarse tune position circuits were used to pretune the VCO immediately on demand to within a fraction of a delta of final frequency.
The present invention overcomes the disadvantage of the prior art by providing a method and apparatus which provides a frequency agile acquisition mode that forces the VCO to the desired frequency regardless of large frequency errors.